Mathematical operations may be performed using either a floating-point format or a fixed-point format. A floating-point format offers a higher dynamic range than a fixed-point format by representing a number with a combination of a sign, a mantissa and an exponent. A floating-point format is often implemented according to the IEEE-754 standard for floating-point arithmetic, where the mantissa is a normalized number between 1 and 2, and scaled by a power of 2, as dictated by the exponent. The sign indicates whether the number is negative or positive. The floating-point format is used for a number of reasons. For example, floating-point mathematical operations avoid the need to perform analysis or simulation to identify the scaling necessary to keep numbers in a fixed-point range. Further, when a problem is ill conditioned, the use of floating-point arithmetic may lead to a numerically superior solution, for example, without the need to greatly increase fixed-point word length.
Floating-point mathematical operations provide a dynamic range which allows some algorithms to be reformulated with fewer operations. Floating-point mathematical operations may also obtain the same dynamic range as fixed-point with fewer bits. Accordingly, the underlying floating-point components may be smaller than components for fixed-point operations. On programmable devices where multiplier size is predefined, for example, where a multiplier takes 18 inputs, an 18-bit multiplier used to implement a floating-point format may provide a greater dynamic range than an 18-bit fixed-point multiplier on its own, thus avoiding the need for four multipliers to be combined to get a greater word length. For a given dynamic range, floating-point mathematical operations require fewer bits, thereby reducing the storage and memory bandwidth requirements. In some graphics applications, a 16-bit representation is used. For example, graphics cards may use a 16-bit floating-point format having an 11-bit mantissa and 5-bit exponent to obtain high dynamic range within the packing constraints of 32 and 64-bit memories.
Mathematical operations requiring floating-point or fixed-point formats may be implemented in any type of circuit, such as an integrated circuit. While integrated circuits are typically designed for a particular application, one type of integrated circuit which enables flexibility is a programmable logic device (PLD). A PLD is designed to be user-programmable so that users may implement logic designs of their choices. One type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” having a two-level AND/OR structure connected together and to input/output (I/O) resources by an interconnect switch matrix. Another type of PLD is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources according to a routing configuration. For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose. The configuration data bits may be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
However, the cost of performing floating-point arithmetic on an FPGA is considered very high relative to fixed-point arithmetic. Of the basic floating-point operations, addition and multiplication are the most common operations. Of the two, the cost of floating-point multiplication is relatively low compared to fixed-point multiplication. Floating point multiplication is obtained using a fixed-point multiplier with a relatively small amount of additional logic to calculate the exponent and perform a 1-bit normalization and rounding of the mantissa. In contrast, floating-point addition requires shifters to provide alignment and normalization of mantissas, prior to and following the fixed-point addition. These shifters are expensive to implement in an FPGA, and incur substantial additional logic delay over a fixed-point adder. When performing accumulation, the latency may lead to a reduction in sample rate, or an increase in complexity to accommodate the associated latency in another way.
Accordingly, there is a need for an improved circuit for and method of providing a floating-point adder.